In conventional transistor-transistor logic (TTL) and diode-transistor logic (DTL) tristate devices, logical values corresponding to binary "1" and "0" are ordinarily represented at the output by a high level voltage V.sub.oh, for example greater than 2.4 volts, and a low level voltage V.sub.ol, for example less than 0.8 volts. In positive logic, the high level binary "1" is derived from a voltage source V.sub.cc which "sources" the current to the output when a binary "1" is to be delivered by the output gate. When a binary "0" is required at the output, the output gate blocks sourcing current and instead "sinks" the current from the outpout load to ground so that the low level voltage V.sub.ol appears at the output of the logic gate. The high impedance third state is achieved by diverting base drive current from the elements of the device thru an enable gate so that they are all nonconducting and the output V.sub.o effectively becomes a high impedance to any exterior circuitry. Thus, the typical TTL tristate output gate functions by "sinking" and "sourcing" current at the output according to whether a binary "1" (high level voltage) or a binary "0" (low level voltage) is the desired outcome of previously executed logical operations or by exhibiting a high impedance at the output according to the signal at the enable gate. In negative logic the representation of binary 1 and 0 by high and low level voltage is reversed.
A conventional low power Schottky TTL tristate output device is illustrated in FIG. 1. Several elements or stages can be identified in such a TTL output gate. The "pullup" element for sourcing current from the higher level voltage V.sub.cc and delivering binary 1 consists of transistors Q2 and Q3 forming a Darlington transistor pair that can supply a relatively large current between the high level voltage source V.sub.cc and the output V.sub.o when a much smaller current is applied to the base of Q2. The "pulldown" element or stage for sinking current from the output to ground consists of transistor Q4 with a conventional squaring network at its base comprised of resistors R3 and R4 and transistor Q5. The phase splitter element or stage consists of transistor Q1 which receives the data signal input to the gate in the form of a high or low level voltage V.sub.i and controls the pullup and pulldown elements for either sourcing or sinking current at the output V.sub.o as determined by the data signal input to the gate.
When a low level voltage or potential appears at the input V.sub.i, a low voltage also appears at the base of phase splitter transistor Q1 and this transistor is deprived of base drive current so that it no longer conducts current through its collector to emitter thereby turning off pulldown transistor Q4. Ideally, the output of V.sub.o of the gate is therefore isolated from ground. At the same time, because Q1 is non-conducting, the high level voltage V.sub.cc appears at the base of sourcing transistor Q2 supplying base current for transistor Q2 which turns on and supplies current to the base of Q3 which in turn becomes conducting and "sources" amplified current from V.sub.cc to the output V.sub.o. The TTL logic gate is therefore inherently inverting as a binary 0 at the input V.sub.i represented by a low voltage level generates a binary 1 at the output represented by voltage level V.sub.oh.
When a binary 1 appears at the input, current supplies base drive to transistor Q1, Q1 becomes conducting, sinking current from the base of Q2 and therefore turning off the Darlington transistor current source represented by transistors Q2 and Q3. Current from high level voltage V.sub.cc is therefore no longer sourced to the output V.sub.o. At the same time, pulldown transistor Q4 becomes conducting through its collector to emitter to ground as a result of the current supplied to its base and begins to discharge current from whatever load capacitance may be coupled to the output V.sub.o of the gate, bringing the output V.sub.o to a low level potential corresponding to binary 0. While transmitting binary signals, the TTL output is functioning in a bistate mode. A high level potential at the enable gate terminal A "enables" the gate to function in this bistate mode.
As shown in FIG. 1 and in other figures, some of the transistor and diode components are typically Schottky diodes and transistors indicated by the opposite square hooks in the schematic symbols. The Schottky clamping effected by an internal modification in these devices produces quicker turn-off during switching.
The element added in order to create a high impedance third state at V.sub.o is the enable gate at terminal A represented in part by transistor Q9. When the enable gate transistor Q9 is conducting, base current from V.sub.cc to the Darlington transistor pullup element Q2 and Q3 is diverted through the enable gate by way of diode D1 to ground. Similarly, the base current of phase splitter transistor Q1 finds a low impedance path to ground through diode D2 and the collector of enable gate transistor Q9. Ordinarily transistor Q9 is non-conducting so that the aforesaid routes to ground are blocked. In this condition, the output gate functions as a bistate output device in the manner described. The enable gate is generally itself a bistate TTL output device where transistor Q9 forms the pulldown element. A high level potential at enable gate terminal A "enables" the output device to transmit binary signals while a low level potential delivered by the enable gate to terminal A sinks current from the elements of the device.
In order to establish a high impedance third state at V.sub.o and node B connected to the common bus, the enable gate is activated by a signal so that it becomes conducting through Q9 to ground delivering a low potential at terminal A. In this state, the enable gate effectively sinks all current at the elements of the output gate including the pullup and phase splitter stages (and therefore indirectly the pulldown element) by providing a direct route to ground. With all of the elements deprived of base current, the output effectively becomes a high impedance to any exterior circuitry coupled to node B on the common bus. In this condition, the gate should neither source nor sink current at the output and will behave preferably as if nothing were there. Further discussions of TTL tristate output devices is found in copending United States patent applications.
Such a tristate device is therefore particularly applicable and suitable for applications in which a plurality of output gates are tied together or coupled to a common bus structure. In such common bus applications only one output, that is only one of the gates coupled to the bus structure, determines the voltage (high or low) of the bus while the other outputs for the remaining gates are in the high impedance third state. Thus, in a typical application, several tri-state devices 11 have their outputs tied together on a common bus or wire 12 which transmits signals to a receiver or receivers 14 as illustrated in FIG. 2. All but one of these devices is in the high impedance (high Z) state. The remaining device 13 is active. When the active device undergoes a low-to-high transition, a problem is encountered. Although the high Z output devices 11 have high DC impedance, they have a relatively low AC impedance. This is because there exists a parasitic junction capacitance between the base and collector of the output transistor Q4 of each device. When the potential at the common bus rises, and the device is in its high Z state, charge is coupled through this base collector capacitance. Since the squaring network looks like a relatively high impedance most of the feed back goes into the base of Q4. This base current becomes amplified by the common-emitter current gain of the transistor to provide a large collector current into Q4. The effect on the output and node B is equivalent to placing a low impedance at this node for the duration of the transition, or conversely, to place a large capacitance on the common bus. This is undesirable because it slows down the ability of the one active device on the bus to force a low-to-high transition and requires more energy to accomplish a low-to-high transition.
For further explanation of the problem, in the normal bistate mode of operation pulldown transistor Q4 is required to conduct large amounts of current in sinking current from the load. It is therefore physically larger than most of the transistors in the circuit and thus has a large base-collector capacitance. The equivalent circuit showing the effect of this base-collector junction capacitance on transistor Q4 is illustrated in FIG. 1A where the equivalent feedback capacitance accompanying the junction is shown as C.sub.bc connected across the base and collector of transistor Q4. This relatively large base to collector junction capacitance C.sub.bc in the pulldown element transistor is known as the "Miller capacitance." When the voltage or potential at the output or common bus is rising, a significant amount of current i.sub.bc is generated proportional to the rate of change of voltage across the base collector capacitance C.sub.bc. This current is also referred to as the "Miller current." Because of the high resistance of the squaring network, this high resistance represented by R4 in FIG. 1B, some of this Miller current flows into the base of Q4 designated in FIG. 1A as i.sub.b which base current is then multiplied by the gain .beta. of the transistor Q4 resulting in a large collector current i.sub.c =.beta..sub.ib at Q4. This low AC impedance path to ground diverts current from the common bus, reducing the effectiveness of the one active element on the common bus for charging up the load capacitance. As a result, there is wasteful power consumption and retardation or delay in forcing low to high transitions at the common bus.
It is apparent that the current i.sub.b flowing into the base of Q4 must be eliminated to avoid these harmful effects of the Miller current. This base feedback current i.sub.b equals i.sub.bc -i.sub.r, that is the Miller current minus the portion diverted through resistance R4, and this could only be done if i.sub.r were equal to or greater than the Miller current i.sub.cb. However, this condition that i.sub.r be greater than or equal to the Miller current cannot be achieved in the conventional circuit of FIG. 1 because resistance R4 must have such a large value in order to restrict current loss in the bistate mode when the phase splitter is providing base drive current to the pulldown element Q4. Because the Miller current across the Miller capacitance is proportional to the rate of change of potential across it, Q4 will therefore stay on until the voltage at the output stops changing from low to high. During this time, considerable current passes to ground from the common bus through the now conducting pulldown transistor wasting power.
Further background on transistor logic tristate output devices is found in copending U.S. patent application Ser. No. 005,929, filed Jan. 24, 1979, entitled "Transistor Logic Tristate Output With Reduced Power Dissipation," Steven N. Goodspeed, inventor; and copending Patent Application Ser. No. 005,928, filed Jan. 24, 1979, now U.S. Pat. No. 4,255,670, entitled "Transistor Logic Tristate Output With Feedback," Paul J. Griffith, inventor; both of said applications assigned to the assignee of the present invention. Further background on the problem of parasitic Miller capacitance and Miller feedback current is found in copending U.S. patent application Ser. No. 034,380, filed Apr. 30, 1979, entitled "Transistor Logic Output for Reduced Power Consumption and Increased Speed During Low to High Transition," Robert W. Bechdolt, inventor; and patent application Ser. No. 065,991, filed Aug. 13, 1979, entitled "Transistor Logic Output Device For Diversion of Miller Current," Paul J. Griffith, inventor; both said applications also assigned to the assignee of the present invention, namely Fairchild Camera Instrument Corporation, Mountain View, Calif.